SystemVerilog Modport

  • The Modport specifies the port directions to the signals declared within the interface.
  • Modports can have, input, output, inout and ref.
  • Modports are declared inside the interface with the keyword modport.
  • Modport provides access restrictions by specifying the port directions.
  • The keyword modport indicates that the directions are declared as if inside the module.

Necessity of Modport :

By default, Nets and variables in the interface are accessible with direction as inout. Any module that are connected to interface net, can either drive or sample the values. Consider testbench and DUT are driving the value in both end at the same time. The result comes with X on the net/variable. To overcome this issue, Modport is used.

Declaration :

The below code shows the declaration of modport inside the interface

logic a;
logic b;
modport dut (input a, output b);
modport tb (input a, input b);

Modport wire declared with input is not allowed to drive or assign, any attempt to drive leads to a compilation error.

Example :

interface mod_port();
//declaring the signals
logic [3:0] a;
logic [3:0] b;
logic [6:0] c;
modport tb (output a, b, input c);