Common Datatypes (Verilog & Systemverilog)
Datatype | State | Signed/Unsigned | Number of bits | Example |
---|---|---|---|---|
reg | 4 | Unsigned | Atleast 1 bit | |
wire | 4 | Unsigned | Atleast 1 bit | |
integer | 4 | Signed | Greaterthan or equal to 32 (>=32) | |
real | - | - | - | |
time | - | - | - | |
realtime | - | - | - |
Datatypes Introduced in systemverilog
Datartypes | State | Signed/Unsigned | Number of bits | Example |
---|---|---|---|---|
logic | 4 | Unsigned | Atleast 1 bit | |
bit | 2 | Unsigned | Atleast 1 bit | |
byte | 2 | Signed | 8 | |
shortint | 2 | Signed | 16 | |
int | 2 | Signed | 32 | |
longint | 2 | Signed | 64 | |
shortreal | - | - | - |