Clocking Block

Clocking blocks have been introduced in SystemVerilog to address the problem of specifying the timing and synchronization for a group of signals in a testbench.

A clocking block is a collection of signals synchronized on a particular clock and makes their timing explicit. It basically separates the time related details from the structural, functional and procedural elements of a testbench.

Clocking blocks can only be declared inside a module, interface or program.

A Clocking block defined between clocking and endclocking keyword pair.

Clocking block declaration

clocking clock @(posedge clk);
default input #2ns output #3ns;
input a1, a2;
output b1;

Input and Output Skews

  • Input signals are sampled at the designated clock edge and outputs signals are driven at clock edge in a cycle.
  • If an input skew is specified then the signal is sampled at skew time units before the clock event.
  • If output skew is specified, then output (or inout) signals are driven skew time units after the corresponding clock event.

A skew must be a constant expression and can be specified as a parameter. In case if the skew does not specify a time unit, the current time unit is used.

Cycle Delay

The ## operator can be used to delay execution by a specified number of clocking events, or clock cycles.


## 2; // wait for 2 clock cycles

Clocking block events

The clocking event can be accessed directly by using the clocking block name.

clocking john @(posedge clk);
default input #2ns output #3ns;
input a1, a2;
output b1;

The clocking event of the john clocking block can be used to wait for that particular event:


Individual signals from the clocking block can be accessed using the clocking block name and the dot (.) operator. All events are synchronized to the clocking block.